1. Field of the Invention
The present invention relates to a data strobe output buffer and a memory device, and more particularly to a data output buffer, data strobe output buffer and a memory device performing a pre-emphasis function for compensating for data loss on a transmission line.
2. Description of the Related Art
As operating speeds of a computer system and a network system continue to increase, memory devices such as DRAM devices require an ever-larger large capacity and require operation at higher rates. In a computer system, a central processing unit (CPU) and memory are interconnected via a memory controller. The memory may include a memory module that is mounted in a connector slot, which is manufactured on a motherboard. The memory controller and the memory module are electrically coupled through a transmission line formed on a printed circuit board (PCB). Therefore, signal attenuation on the transmission line may be increased as a distance increases between the memory controller and the memory module.
One technique for reducing the effects of signal reflection on the transmission line is to use a termination resistor coupled to a termination voltage, which is referred to as a termination.
In a DDR2 memory module, an on die termination (ODT) may be adopted such that the termination resistor installed in each DRAM chip of a module in a stand-by mode is activated, and the termination resistor of the module in an active mode is deactivated so that the termination resistor of the module in the stand-by mode may serve as the termination resistor of the module in the active mode. Using the on die termination technique, simpler interconnections on the motherboard may be achieved.
FIG. 1 is a circuit diagram illustrating a conventional push-pull data output buffer and FIG. 2 is a timing diagram illustrating an operation of the push-pull data output buffer of FIG. 1.
Referring to FIG. 1, a transmitter chip 100 outputs an internal data signal DATA to an output terminal 104 via the push-pull data output buffer 102. The output terminal 104 is coupled to a termination resistor RTT through a transmission line 106 and the termination resistor RTT is coupled to a supply voltage VDDQ.
A receiver chip 110 receives a signal at an input buffer 112 through the transmission line 106. The input signal is compared with a reference voltage VREF to determine whether a received signal is in a logic “high” state or logic “low” state.
When the transmitter chip 100 outputs a signal having the logic “high” state, the data signal DATA has a logic “low” state so that a pull-up transistor PUD of the output buffer 102 is turned on and a pull-down transistor PDD is turned off. Therefore, the output terminal 104 receives a power supply voltage VDDQ through the pull-up transistor PUD and also through the termination resistor RTT so that an output voltage DQ at the output terminal 104 is rapidly increased to a voltage level approximating about VDDQ.
When the transmitter chip 100 outputs a signal having the logic “low” state, the data signal DATA has a logic “high” state so that the pull-up transistor PUD is turned off and the pull-down transistor PDD is turned on. Therefore, the output terminal 104 receives a power supply voltage VSSQ through the pull-down transistor PDD so that an output voltage DQB at the output terminal 104 is decreased slower than a rising rate of the output voltage DQ to a voltage level VOL, which is expressed as the following equation 1.VOL=(VDDQ−VSSQ)×RONPDD/(RONPDD+RTT+RTL)  [Equation 1]
Herein, RONPDD is the turn-on resistance of the pull-down transistor PDD and RTL is the resistance of the transmission line. Therefore, an intersection point of a rising transition of the output voltage DQB and a falling transition of the output voltage DQ is higher than the reference voltage VREF, which is depicted in area A in FIG. 2. Namely, a skew may be generated between the rising transition and the falling transition of the data output signal so that signal integrity is degraded.
To overcome the above problem, a conventional approach is used to delay an enable signal applied to the output buffer when data is driven high relative to when the data is driven low so that a rising transition and a falling transition of the enable signal may intersect at the reference voltage level VREF.
However, the conventional approach is based on controlled timing so that a predefined amount of delay may vary depending on variances in process, power supply voltage, temperature, etc. The change in the amount of delay caused by the variance of the respective parameters may affect a timing characteristic including tDQSQ (skew between output data signal and RDQS signal) of the memory.
In a high-speed synchronous semiconductor memory device, a data strobe signal DQS is used to reduce the skew of data. The DQS signal is output through a data strobe signal output buffer. The data strobe signal output buffer may include a push-pull circuit that is controlled by a tri-state of a high impedance state, a logic high state and a logic low state.
FIG. 3 is a timing diagram illustrating a conventional data strobe signal.
Referring to FIG. 3, the data strobe signal (or DQS signal) may be divided into a preamble (represented as section A in FIG. 3), a time interval of toggling the DQS signal based on the clock signal (represented as section B in FIG. 3) and a postamble (represented as section C in FIG. 3). Compared with the sections B and C, the data strobe signal in the section A has a lower voltage level because the data strobe signal is driven low for a longer time period. Therefore, a first rising transition of the DQS signal in the section A is delayed so that a pulse width W1 of a first pulse of the DQS signal may be shorter than another pulse width W2.
Therefore, in a memory controller that receives data in synchronization with the data strobe signal, the decrease in the pulse width of the data strobe signal may cause difficulty in ensuring secure receipt of the data (e.g., D0). Therefore, signal integrity of the data (e.g., D0) may be degraded.